How to: compile to single file

Hello,

1. yes, you can put a complete pojekt in one VHDL or Verilog file, if this seems meaningful to you.

2. why don't you just try?

Regards,

Frank

Hi,

The project is made with QuartusII, and I need to export the entire project to another designer, who is not using Quartus. So I would like to compile the project and get a single file. Because I used Quartus I have the graphical view instead of port maps. Somehow it must be possible to see the portmap fil (i guess quartus is generating this file). Can anyone help?

Regards,

Morten

Open the graphical file(the top level design)

and then select from the menu

File ->

Create/update ->

create hdl file for current file.

thats it.

Hello,

create hdl file for current file is the basic operation to convert graphical (*.bdf) top levels to VHDL or Verilog. Depending on your design there may be additional manual steps necessary.

1. In a bdf-file, non-VHDL compatible port naming could have be used, e. g. pin1-3. It must be changed to VHDL conform names (case insensitive alphanum_underline without leading digits).

2. If Megawizard lpm functions have been used in graphics, for the AHDL megafunction wrapper a equivalent VHDL version must be generated by Megawizard or, what I prefer, replaced by a direct instantiation of the Megafunction VHDL library.

Finally, all VHDL sources must be merged manually, if a single file is needed.

Regards,

Frank