How to: compile to single file

Hello,

create hdl file for current file is the basic operation to convert graphical (*.bdf) top levels to VHDL or Verilog. Depending on your design there may be additional manual steps necessary.

1. In a bdf-file, non-VHDL compatible port naming could have be used, e. g. pin1-3. It must be changed to VHDL conform names (case insensitive alphanum_underline without leading digits).

2. If Megawizard lpm functions have been used in graphics, for the AHDL megafunction wrapper a equivalent VHDL version must be generated by Megawizard or, what I prefer, replaced by a direct instantiation of the Megafunction VHDL library.

Finally, all VHDL sources must be merged manually, if a single file is needed.

Regards,

Frank