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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to: compile to single file

Hi, I have a hierarchically project with several VHDL files. Is it possible to make 1 single file, that contains everything (Portmaps, entity, architechures, processes etc.)? Hopefully a VHDL file...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

The project is made with QuartusII, and I need to export the entire project to another designer, who is not using Quartus. So I would like to compile the project and get a single file. Because I used Quartus I have the graphical view instead of port maps. Somehow it must be possible to see the portmap fil (i guess quartus is generating this file). Can anyone help?

Regards,

Morten