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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to: compile to single file

Hi, I have a hierarchically project with several VHDL files. Is it possible to make 1 single file, that contains everything (Portmaps, entity, architechures, processes etc.)? Hopefully a VHDL file...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

1. yes, you can put a complete pojekt in one VHDL or Verilog file, if this seems meaningful to you.

2. why don't you just try?

Regards,

Frank