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Altera_Forum
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14 years ago

How to align an output clock mux to 2 inputs clocks

Hi,

I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200.

My problem is coming from the usage of clocks muxes inside ASIC :mad:

Basically, they use a simple 2 inputs (clk1 and clk2) / 1 output (clk_switch) classic mux with 1 selection signal (sel_clk) to mux 2 clocks signals.

The need is that the resulting output clock clk_switch must be aligned either with the clk1 when sel_clk is 0 and with clk2 when sel_clk is 1.

It seems to be very easy onto ASIC :( but in a FPGA :confused:

Is there a way to constraints Quartus to do such things ? (by adding good delay before the GLOBAL for instance ...)

How ? Using Sdc ? What i need to constraints/declare ?

A little quartus example is really welcome ... if possible.

My project is onto Quartus 9.1 sp1 with timequest.

Note that CLK1, CLK2 and CLK_SWITCH need to be on FPGA clocks trees too (there is a large amount of FFs usings theses 3 clocks).

Thanks a lot.

Regards.

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    What does align refers to ? syn to rising or falling?

    There is a megafunction called altclkctrl to implent clk mux. It is a hard ip. Or you can add some logic to align it with the clock. Basically just use a AND gate and flops will do. You can find it in internet.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Is is align to rising edge.

    I don't see how to add a gate ... how to be sure that clocks, in fact rising edge, are aligned ????

    A simple quartus example with a clock muxes, some FF clocked onto CLK1, others onto CLK2, and others onto clk_switch is welcome ...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    PLLs are able to switch clocks, so I believe there's a hardcore for such thing.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    A precision. CLK1 and CLK2 are not direct INPUT pads of the FPGA !!!

    They are internal (generated) clocks ...

    So, how can i use the pll .???? i don't see.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Why do You need to generate clocks? Clock generation can be achieved only using PLL, otherwise use clock enables.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I remeber you that this is an ASIC PROTOTYPING so i cannot do what i want ...

    I need to make working the ASIC design in the FPGA without changing the VHDL ... as much as possible ...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    FPGA is not the same as ASIC, so You'll have to deal with it and its rules.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I struggle with that since 10 years :)

    So, you confirm that there is no possibility to align output clock to the 2 inoput clocks ?

    Even adding specific timing delay (mindelay/maxdelay/), global position, ... or something else in timequest sdc.

    Regards.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I've made a small example which might fulfill your req's,

    the idea is that your internally generated clocks (e.g 100MHz & 66Mhz) are replaced

    with clocks generated by a pll, 100 & 66 MHz,

    both pll outputs also go to clk_mux - altera megawizard ALTCLKCTRL module,

    which works as the clock mux,

    and both pll outputs go to "stratixiii_clkena" clock buff to compensate multiplexing

    delay [in case quartus is not smart enough to insert the buffs itself];

    in the example cnt_100, cnt_66 mimics modules working with 100 and 66 clocks,

    cnt_sw works with 'switchable' clock; 

    
module clk_switch
(  input            ext_clk,  switch,
   output reg  cnt_100, cnt_66, cnt_sw
);
wire c100, c66;
wire sys_clk100, sys_clk66, sys_clk_sw;
 pll pll_i
       ( .inclk0(ext_clk), .c0(c100), .c1(c66) );
 stratixiii_clkena buff100
  ( .ena(1'b1), .enaout(),
    .inclk(c100), .outclk(sys_clk100) );
	
 stratixiii_clkena buff66
  ( .ena(1'b1), .enaout(),
    .inclk(c66), .outclk(sys_clk66) );	
	
 clk_mux clock_mux
    ( .clkselect(switch), .inclk0x(c100), .inclk1x(c66),
      .outclk(sys_clk_sw) );
 always @(posedge sys_clk100)
   cnt_100 <= cnt_100 + 1'b1;
 always @(posedge sys_clk66)
   cnt_66 <= cnt_66 + 1'b1;   
 always @(posedge sys_clk_sw)
   cnt_sw <= cnt_sw + 1'b1;   
   
endmodule

    ----

    have fun j_andr