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Honored Contributor
Honored ContributorHow to align an output clock mux to 2 inputs clocks
Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_ForumHonored Contributor
Honored ContributorWhat does align refers to ? syn to rising or falling?
There is a megafunction called altclkctrl to implent clk mux. It is a hard ip. Or you can add some logic to align it with the clock. Basically just use a AND gate and flops will do. You can find it in internet.
