How to align an output clock mux to 2 inputs clocks

I've made a small example which might fulfill your req's,

the idea is that your internally generated clocks (e.g 100MHz & 66Mhz) are replaced

with clocks generated by a pll, 100 & 66 MHz,

both pll outputs also go to clk_mux - altera megawizard ALTCLKCTRL module,

which works as the clock mux,

and both pll outputs go to "stratixiii_clkena" clock buff to compensate multiplexing

delay [in case quartus is not smart enough to insert the buffs itself];

in the example cnt_100, cnt_66 mimics modules working with 100 and 66 clocks,

cnt_sw works with 'switchable' clock;

module clk_switch
(  input            ext_clk,  switch,
   output reg  cnt_100, cnt_66, cnt_sw
);
wire c100, c66;
wire sys_clk100, sys_clk66, sys_clk_sw;
 pll pll_i
       ( .inclk0(ext_clk), .c0(c100), .c1(c66) );
 stratixiii_clkena buff100
  ( .ena(1'b1), .enaout(),
    .inclk(c100), .outclk(sys_clk100) );
	
 stratixiii_clkena buff66
  ( .ena(1'b1), .enaout(),
    .inclk(c66), .outclk(sys_clk66) );	
	
 clk_mux clock_mux
    ( .clkselect(switch), .inclk0x(c100), .inclk1x(c66),
      .outclk(sys_clk_sw) );
 always @(posedge sys_clk100)
   cnt_100 <= cnt_100 + 1'b1;
 always @(posedge sys_clk66)
   cnt_66 <= cnt_66 + 1'b1;   
 always @(posedge sys_clk_sw)
   cnt_sw <= cnt_sw + 1'b1;   
   
endmodule 

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have fun j_andr