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Altera_Forum
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14 years ago

How to align an output clock mux to 2 inputs clocks

Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I remeber you that this is an ASIC PROTOTYPING so i cannot do what i want ...

I need to make working the ASIC design in the FPGA without changing the VHDL ... as much as possible ...