Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to align an output clock mux to 2 inputs clocks
Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_ForumHonored Contributor
Honored ContributorI remeber you that this is an ASIC PROTOTYPING so i cannot do what i want ...
I need to make working the ASIC design in the FPGA without changing the VHDL ... as much as possible ...
