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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to align an output clock mux to 2 inputs clocks

Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I struggle with that since 10 years :)

So, you confirm that there is no possibility to align output clock to the 2 inoput clocks ?

Even adding specific timing delay (mindelay/maxdelay/), global position, ... or something else in timequest sdc.

Regards.