Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How to align an output clock mux to 2 inputs clocks

Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is is align to rising edge.

I don't see how to add a gate ... how to be sure that clocks, in fact rising edge, are aligned ????

A simple quartus example with a clock muxes, some FF clocked onto CLK1, others onto CLK2, and others onto clk_switch is welcome ...