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Honored Contributor
Honored ContributorHow to align an output clock mux to 2 inputs clocks
Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_ForumHonored Contributor
Honored ContributorWhy do You need to generate clocks? Clock generation can be achieved only using PLL, otherwise use clock enables.
