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Honored Contributor
Honored ContributorHow to align an output clock mux to 2 inputs clocks
Hi, I'm in charge of prototyping an ASIC into an FPGA altera Stratix3sl200. My problem is coming from the usage of clocks muxes inside ASIC :mad: Basically, they use a simple 2 inputs...
Altera_ForumHonored Contributor
Honored ContributorA precision. CLK1 and CLK2 are not direct INPUT pads of the FPGA !!!
They are internal (generated) clocks ... So, how can i use the pll .???? i don't see.
