Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp needed for this 3 bit parity generator/checker.
:cry: Im a total Noob and seriously need help in my VHDL.
the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_out and even_out). When the number of high level input is odd, odd_out is kept HIGH and even_out output LOW. Likewise, if the number of high level input is even, even_out is kept HIGH and odd_out LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.12 Replies
Altera_Forumthis is what i've done. but obviously it doesnt work.
ENTITY I1 IS PORT( c : IN std_logic; b : IN std_logic; a : IN std_logic; odd_out : OUT std_logic; even_out : OUT std_logic); END I1; ARCHITECTURE arc OF I1 IS BEGIN process (a, b, c) Begin If (a ='1', b ='0', c ='0') then odd_out <= "1", even_out <= "0"; If (a ='0', b ='1', c ='0') then odd_out <= "1", even_out <= "0"; If (a ='1', b ='1', c ='0') then odd_out <= "0", even_out <= "1"; If (a ='0', b ='0', c ='1') then odd_out <= "1", even_out <= "0"; If (a ='1', b ='0', c ='1') then odd_out <= "0", even_out <= "1"; If (a ='0', b ='1', c ='1') then odd_out <= "0", even_out <= "1"; If (a ='1', b ='1', c ='1') then odd_out <= "1", even_out <= "0"; else odd_out <= "0", even_out <= "0"; HELPP! my hair is falling.- Altera_Forum
Use the xor operation to get the parity : (a xor b xor c) will be one if you have an odd number of inputs active.
- Altera_Forum--- Quote Start --- ...and treat C as the MSB --- Quote End --- What does this mean? From your code you have three 1 bit inputs. I don't see the MSB.
- Altera_Forum
the truth table and the waveform of the finalised answer is attached. C is the MSB then B, and then A as the LSB.
- Altera_Forum
thanks LETS. but i have not learnt how to execute the xor operation in vhld, i am only told to make the vhld to have the result of the waveform i attached in the previous post. :)
- Altera_Forum
change all the lines:
then odd_out <= "1", even_out <= "0"; to then odd_out <= "1"; even_out <= "0"; - Altera_Forum
The xor is a basic operation like not, or, and. Here is how it looks like :
There is a signal inside the architecture because the even_out signal is the complementary of the odd_out signal but you cannot read an output, so you cannot write directly : even_out <= not odd_even.entity I1 is port ( c : in std_logic; b : in std_logic; a : in std_logic; odd_out : out std_logic; even_out : out std_logic ); end I1; architecture arc of I1 is signal result : std_logic; begin process (a, b, c) begin result <= a xor b xor c; odd_out <= result; even_out <= not result; end process; end arc; - Altera_Forum--- Quote Start --- There is a signal inside the architecture because the even_out signal is the complementary of the odd_out signal but you cannot read an output, so you cannot write directly : even_out <= not odd_even. --- Quote End --- It is not simply the inverse, because if all A,B and C are '0', then odd and even out are '0'. The state table is very similar to a full adder, with even out being Sum and odd out_out being carry, but the A, B, C = '1' case makes it different.
- Altera_Forum
Tricky, i'll try it out tmr. because the programmes are in sch. thanks for the advice.
anyway, process (a,b,c) gives and error saying no aggregates is found. LETS thanks also. :) - Altera_Forum--- Quote Start --- It is not simply the inverse, because if all A,B and C are '0', then odd and even out are '0'. The state table is very similar to a full adder, with even out being Sum and odd out_out being carry, but the A, B, C = '1' case makes it different. --- Quote End --- You're right Tricky, I read the truth table to fast. So you can add an "if" for the particular case and the operation for the rest.
