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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help needed for this 3 bit parity generator/checker.

:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Tricky, i'll try it out tmr. because the programmes are in sch. thanks for the advice.

anyway,

process (a,b,c) gives and error saying no aggregates is found.

LETS thanks also. :)