Help needed for this 3 bit parity generator/checker.

this is what i've done. but obviously it doesnt work.

ENTITY I1 IS

PORT(

c : IN std_logic;

b : IN std_logic;

a : IN std_logic;

odd_out : OUT std_logic;

even_out : OUT std_logic);

END I1;

ARCHITECTURE arc OF I1 IS

BEGIN

process (a, b, c)

Begin

If (a ='1', b ='0', c ='0')

then odd_out <= "1", even_out <= "0";

If (a ='0', b ='1', c ='0')

then odd_out <= "1", even_out <= "0";

If (a ='1', b ='1', c ='0')

then odd_out <= "0", even_out <= "1";

If (a ='0', b ='0', c ='1')

then odd_out <= "1", even_out <= "0";

If (a ='1', b ='0', c ='1')

then odd_out <= "0", even_out <= "1";

If (a ='0', b ='1', c ='1')

then odd_out <= "0", even_out <= "1";

If (a ='1', b ='1', c ='1')

then odd_out <= "1", even_out <= "0";

else

odd_out <= "0", even_out <= "0";

HELPP! my hair is falling.