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Altera_Forum
Honored Contributor
Honored ContributorHelp needed for this 3 bit parity generator/checker.
:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_ForumHonored Contributor
Honored ContributorThe xor is a basic operation like not, or, and. Here is how it looks like :
entity I1 is
port
(
c : in std_logic;
b : in std_logic;
a : in std_logic;
odd_out : out std_logic;
even_out : out std_logic
);
end I1;
architecture arc of I1 is
signal result : std_logic;
begin
process (a, b, c)
begin
result <= a xor b xor c;
odd_out <= result;
even_out <= not result;
end process;
end arc;
