Help needed for this 3 bit parity generator/checker.

The xor is a basic operation like not, or, and. Here is how it looks like :

entity I1 is
    port
    (
        c : in std_logic;
        b : in std_logic;
        a : in std_logic;
        odd_out : out std_logic;
        even_out : out std_logic
    );
end I1;
architecture arc of I1 is
signal result : std_logic;
begin
    process (a, b, c)
    begin
        result <= a xor b xor c;
        odd_out <= result;
        even_out <= not result;
    end process;
end arc;