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Altera_Forum
Honored Contributor
Honored ContributorHelp needed for this 3 bit parity generator/checker.
:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ...and treat C as the MSB --- Quote End --- What does this mean? From your code you have three 1 bit inputs. I don't see the MSB.
