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Altera_Forum
Honored Contributor
Honored ContributorHelp needed for this 3 bit parity generator/checker.
:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_ForumHonored Contributor
Honored Contributorthe truth table and the waveform of the finalised answer is attached. C is the MSB then B, and then A as the LSB.
