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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help needed for this 3 bit parity generator/checker.

:cry: Im a total Noob and seriously need help in my VHDL. the question: To design a 3-bit parity generator/checker that has three data inputs (A to C) and two odd/even parity outputs (odd_o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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There is a signal inside the architecture because the even_out signal is the complementary of the odd_out signal but you cannot read an output, so you cannot write directly : even_out <= not odd_even.

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It is not simply the inverse, because if all A,B and C are '0', then odd and even out are '0'. The state table is very similar to a full adder, with even out being Sum and odd out_out being carry, but the A, B, C = '1' case makes it different.