Help needed for this 3 bit parity generator/checker.

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There is a signal inside the architecture because the even_out signal is the complementary of the odd_out signal but you cannot read an output, so you cannot write directly : even_out <= not odd_even.

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It is not simply the inverse, because if all A,B and C are '0', then odd and even out are '0'. The state table is very similar to a full adder, with even out being Sum and odd out_out being carry, but the A, B, C = '1' case makes it different.