HDL import not supported for tri0

Hi,

I am seeking some input for the following scenario.

I have recently used Quartus to create a Remote Update module using Verilog. The plan was to import this into Simulink, because our firmware is developed in that environment.

Using Simulink's importhdl function the relevant files began to parse until it reached the Tri-State declaration 'tri0' in the altera_remote_update_core.v file which is not supported.

Is it possible to mask this at all?

Or, would it be pointless to even try considering it forms the RU core?

Lastly, I have read that enabling the RSU internal circuitry is done by selecting the Assignments tab and then clicking on the Device. I am using Quarus Prime Lite edition, which has most of the options under the Assignments tab 'Greyed' out.

Does the ability to use the RSU internal circuity depend on having Quartus Prime 'Standard' edition if using Cyclone IV and/or V FPGA's?

Regards,

Dan