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sbj's avatar
sbj
Icon for New Contributor rankNew Contributor
1 day ago

GTS Transceiver PLL Usage

From the GTS Transceiver PHY User Guide:

“The GTS System PLL Clocks IP cannot be compiled or simulated as a standalone IP. It must always connect to the GTS PMA/FEC Direct PHY IP.”

  • Does this restriction also apply when the parameter “Use case of System PLL” is set to “FABRIC_USE_CASE”?
  • In this mode:
    • Is it mandatory to use output clock C1 to drive the FPGA fabric?
    • Are there other usable outputs?
  • How can we determine the set of available output frequencies for C1?
    • What is the relationship between the output frequency and the selected reference clock (refclk)?
Configuration
Core Logic
Programmable Logic Device

1 Reply

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 hours ago

    Hi,

     

    The actual guidance is "When you use the GTS System PLL Clocks IP, it must always connect to the GTS PMA/FEC Direct PHY IP or protocol IPs." Essentially meaning that C0 port of the IP must be connected to logic and cannot be left unconnected.

    When “Use case of System PLL” is set to “FABRIC_USE_CASE”, by default C0 output is enabled for fabric use. If you need another output driving the fabric, you have to set "Output frequency C1 enable" to "On". 

    To determine the output frequency of C1, use the drop-down menu in the IP. The options depends on the input refclk frequency that you set. Internally, the VCO frequency is calculated based on both input and both the output clock requirements and a range of available drop-down values is restricted due to multiplication and division factors possible.

     

    Regards