glitich in the outputs

you dont want to slow the clock, you want to generate clock enables so that things only change when the enable is active. Dividing the clock (without a PLL, which wont work at low frequencies) will cause setup and hold violations.

THANK YOU FOR THE REPLY,, according to the codes you have seen already, as i am downloading these codes to the FPGA , and the changes of LEDs need to be slow to be recognized by human vision, and the board has 50Mhz CLOCK, how to add some codes to the existing codes to divide the clcok rather than using manual bushbutton as clcok, so i can use the internal clock of the FPGA,,

Here is the attached file

you can only do that by doing an RTL simulation - you will need modelsim to do that, rather than the Quartus Simulator.

yes you are right, i did compile the wrong codes, now everything is ok no more glitches, they are disappeared after the outputs are registred.

post the output waveform.

I used one process as you advised, but unfortunately the glitches still exist , i am not sure what is the reason, i am simulating using quartus ii with DE2 board selected

thank you too much for the help, it is highly apprecaited

there is nothing wrong with 1 process style - it can actually help prevent errors. Plus it would register all your outputs for you. I think older books only recommend the 2 process style because at the time compilers were pretty crap at doing anything with source code outside a few templates. Now they are much much better.

Library ieee;
use ieee.std_logic_1164.all;
PORT (Right,Left,Hazard : IN STD_LOGIC;
  Clk, Reset : IN STD_LOGIC;
  LA,LB,LC : OUT STD_LOGIC;
  RA,RB,RC : OUT STD_LOGIC);
END Vehicle_Tail_Lights_control;
ARCHITECTURE state_machine OF Vehicle_Tail_Lights_control IS
  TYPE state_type IS (Idle,L1,L2,L3,R1,R2,R3,LR3);
  attribute ENUM_ENCODING: STRING;
  attribute ENUM_ENCODING of state_type: type is
  "000 001 011 010 101 111 110 100";
  SIGNAL current_state : state_type;
BEGIN
 
  PROCESS(clk, reset)
  BEGIN
    if reset = '1' then
      current_state <= idle;
      
    elsif rising_edge(clk) then
      
      CASE current_state IS
        WHEN idle =>
          Lc<='0';Lb<='0';La<='0';Ra<='0';Rb<='0';Rc<='0';
          IF ( (Hazard='1') OR ((Left='1') AND (Right='1')))
          THEN current_state <= LR3;
          ELSIF ( (Hazard='0') AND (Left='0') AND (Right='1'))
          THEN current_state <= R1;
          ELSIF ((Hazard='0') AND (Left='1') AND (Right='0'))
          THEN current_state <= L1;
          ELSE
            current_state <= Idle;
          END IF;
            
        WHEN L1 =>
          Lc<='0';Lb<='0';La<='1';Ra<='0';Rb<='0';Rc<='0';
          IF (Hazard = '1') THEN current_state <= LR3;
          ELSE current_state <= L2;
          END IF;
            
        WHEN L2 =>
          Lc<='0';Lb<='1';La<='1';Ra<='0';Rb<='0';Rc<='0';
          IF (Hazard = '1') THEN current_state <= LR3;
          ELSE current_state <= L3;
          END IF;
            
        WHEN L3 =>
          Lc<='1';Lb<='1';La<='1';Ra<='0';Rb<='0';Rc<='0';
          current_state <= Idle;
          
        WHEN R1 =>
          Lc<='0';Lb<='0';La<='0';Ra<='1';Rb<='0';Rc<='0';
          IF (Hazard = '1') THEN current_state <= LR3;
          ELSE current_state <= R2;
          END IF;
            
        WHEN R2 =>
          Lc<='0';Lb<='0';La<='0';Ra<='1';Rb<='1';Rc<='0';
          IF (Hazard = '1') THEN current_state <= LR3;
          ELSE current_state <= R3;
          END IF;
            
        WHEN R3 =>
          Lc<='0';Lb<='0';La<='0';Ra<='1';Rb<='1';Rc<='1';
          current_state <= Idle;
          
        WHEN LR3 =>
          Lc<='1';Lb<='1';La<='1';Ra<='1';Rb<='1';Rc<='1';
          current_state <= idle;
          
      END CASE;
    end if; --clk
  END PROCESS;
END state_machine;

thank you for the reply, as i have read 1 process template is not good choice , i just read it ins ome books that is why i did not use it.