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Altera_Forum's avatar
Altera_Forum
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13 years ago

Gate timing simulation with ModelSim Altera

Dear all,

I'm using quartusII to synthesize my design.

I want to run gate-timing-simulation with ModelSim-Altera.

I did the following steps :

1- Synthesize design with Quartus II

2- Get the output netlist (*.vo) and delay information (*.sdo)

3- Start ModelSim-Altera and run simulation with this netlist and delay (*.sdo)

However, ModelSim-Altera informed that it was fail in loading design.

I want to run test-pattern (that I have run with RTL) with gate-level netlist.

Could anyone help me to solve this issue ?

(Do I miss some steps or are there any error in my way)

Thank you so much !

Best regards,

Thanh Tran.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    What other information did the Modelsim console give you when it had an error?

  • Altera_Forum's avatar
    Altera_Forum
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    Dear all,

    I would like to give you more detail about my problem :

    1- EDA setting :

    A- Design Entry/Synthesis : None

    B- Simulation : ModelSim-Altera - Verilog HDL

    C- Timing Analysis : None

    D- Formal Verification : None

    E- Board-Level : all None

    2- I create a project, and compile it successfully.

    3- After finishing compiling, I start gate-level simulation :

    Tools -> Run Simulation Tool -> Gate Level Simulation

    -> ModelSim is started and compile the design.

    4- ModelSim is started with the following messages :

    # Reading D:/altera/11.1/modelsim_ase/tcl/vsim/pref.tcl # do addersubstractor_run_msim_gate_verilog.do # if {[file exists gate_work]} {# vdel -lib gate_work -all# }# vlib gate_work# vmap work gate_work# Copying d:\altera\11.1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied d:\altera\11.1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vlog -vlog01compat -work work +incdir+. {addersubstractor.vo}# Model Technology ModelSim ALTERA vlog 10.0c Compiler 2011.09 Sep 21 2011# -- Compiling module addersubtractor# # Top level modules:# addersubtractor

    5- Then I start simulation : Simulate -> Start Simulation

    The following errors appear

    # ** Error: (vsim-3033) addersubstractor.vo(3478): Instantiation of 'cycloneii_io' failed. The design unit was not found.# Region: /addersubtractor# Searched libraries:# E:\QuartusII_tutorial\simulation\modelsim\gate_work# ** Error: (vsim-3033) addersubstractor.vo(3514): Instantiation of 'cycloneii_io' failed. The design unit was not found.# Region: /addersubtractor# Searched libraries:# E:\QuartusII_tutorial\simulation\modelsim\gate_work# ** Error: (vsim-3033) addersubstractor.vo(3550): Instantiation of 'cycloneii_io' failed. The design unit was not found.# Region: /addersubtractor# Searched libraries:# E:\QuartusII_tutorial\simulation\modelsim\gate_work# ** Error: (vsim-3033) addersubstractor.vo(3586): Instantiation of 'cycloneii_io' failed. The design unit was not found.# Region: /addersubtractor# Searched libraries:# E:\QuartusII_tutorial\simulation\modelsim\gate_work# ** Error: (vsim-3033) addersubstractor.vo(3622): Instantiation of 'cycloneii_io' failed. The design unit was not found.# Region: /addersubtractor# Searched libraries:# E:\QuartusII_tutorial\simulation\modelsim\gate_work# ** Error: (vsim-3033) addersubstractor.vo(3658): Instantiation of 'cycloneii_io' failed. The design unit was not found.# Region: /addersubtractor# Searched libraries:# E:\QuartusII_tutorial\simulation\modelsim\gate_work# Error loading design

    I think that ModelSim dose not understand the library.

    Could you please give me some advices ?

    Thank you,

    Best regards,

    Thanh Tran.
  • Altera_Forum's avatar
    Altera_Forum
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    When you click 'Start Simulation' you are given an options box where you choose your top level module. Select the 'Libraries' tab of this options box and add the library you need for the search path.

    The library will probably be under quartus/modelsim_ase/altera/verilog/

    (or VHDL is your design is in VHDL). Under this path select the folder cycloneii (or cycloneii_io, I haven't go my windows box running right now so I can't check) and add it to the list. This should fix this problem.
  • Altera_Forum's avatar
    Altera_Forum
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    Dear czeh, jacki2ya

    Thank you so much for your answers !

    I can run gate-level-timing simulation now.

    I would like to ask one more question.

    I see that there are some libraries in the "/modelsim_ase/altera/verilog/"

    such as cyclone, cycloneii, cycloneiv,... How can we know which library

    is appropriate to our current design ? (I check the "Flow summary" report of Quartus after I compile the design successfully, I see that the "Family" is cyclone --> Is this the name of library that I should use at gate simulation -> "Family is cycloneiv --> choose cycloneiv)

    Thank you,

    Best regards,

    Thanh Tran.