Gate timing simulation with ModelSim Altera

When you click 'Start Simulation' you are given an options box where you choose your top level module. Select the 'Libraries' tab of this options box and add the library you need for the search path.

The library will probably be under quartus/modelsim_ase/altera/verilog/

(or VHDL is your design is in VHDL). Under this path select the folder cycloneii (or cycloneii_io, I haven't go my windows box running right now so I can't check) and add it to the list. This should fix this problem.