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Altera_Forum's avatar
Altera_Forum
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17 years ago

FPGA Configuration using CPLD!

Hi all,

I have a question need your precious comments.

As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria.

After following AN386, I successfully download and write FPGA image to a CFI flash.

I use NIOSII IDE to programming and NIOSII command shell to read back. The data existed in flash.

After power cycle, the CPLD should start to move data from flash to FPGA but it's not working.

The input clock to PFL is 27MHz as attached qar.

I measure the address pin, there's 2 high level during flash OE period :confused:.

I wonder any one ever using this function and provide me your experience on that.

Thank you!

BRs,

Johnson

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What type of flash memory are you using? I had trouble with S29GLxxxP.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Gee,

    Thanks for replying my problem.

    I am using S29GL512P10xxx.

    The same as yours.

    I also connect that A0 pin to another CPLD pin to measure output pattern.

    The same pattern as I posted.

    BR,

    Johnson
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Johnson,

    The S29GLxxxP needs reset before starting access, and time from power-on or reset to 1st access is longer than previous model. I recommend you to make sure that reset signal is connected to the S29GLxxxp and put a counter in the MAX II so that PFL delays first access.

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Gee,

    Thanks for your comments.

    I will try your suggestion later.

    And I want to share you how I download my FPGA image to flash.

    I used to use this PFL function as described in AN478 in Arria. But it failed writing to flash and I don't know why at that time.

    Later I use CFI interface after initiate a NIOSII and download it using NIOSII EDS and it works.

    I also read that data using NIOSII command shell and measure the address pattern.

    Through that I found the output of PFL is not correct for flash to work properly.

    I will repeat my test on PFL using Arria.

    Thanks for your reply.

    BRs,

    Johnson
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Did you write the configuration data and the options bits to flash using the NIOSII EDS? Are the options bits at the location that the PFL in the CPLD is looking for them? I just had an issue where I had the PFL core looking at the wrong location in flash for the options bits. Reran the megawizard and reprogrammed flash and it worked great.

    As gee said, you need to write a small power-on reset in the cpld design to hold the flash chip in reset for a bit(whatever the data sheet shows). We ran into this when switching from the N part to the P part.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi gmpstr,

    Thanks for sharing.

    I already added that in my current design.

    Yes, I could noticed that there are some data moving out from flash to fpga.

    But the complete configuration cycle was not finished, I could see nStatus and nCONFIG from Arria pulling high and low to indicate the data has error.

    I noticed that the A0 output from MAXII to flash has a 40-ns pulse...as I posted in my previous post.

    Anyway I have a improvement from your inputs, thanks a lot!

    BRs,

    Johnson
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    I try to simulate your design. First the PFL access address 0x20040, where pof version locates, then the address points 0x20041 but it means nothing.

    If you have modeslsim-AE verilog licence, I will upload the testbench.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Gee,

    Thanks for your information regarding simulation.

    I measure the output pattern of nStatus and A0 and noticed that the 40-ns glitch happened during nSTATUS is low.

    Perhaps I have to double check my settings as I tie all PGM pins to GND..

    I saw your simulation output, thanks for your data..

    That would be of great help if you could provide me your testbench.

    BRs,

    Johnson
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Johnson,

    Looking from the simulation result, 40 ns(1 clock) glitch is normal behavior. If you are concerned about PGM pin, please make sure that they are connected directry, without through resister, to GND.

    Regards!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Gee,

    You are right that I could see that in scope and wave form design in Quartus.

    Do you have any idea about FPP with decompression local or remote/

    I don't know exactly how to set my device in which mode.

    And I wonder how PFL load configuration data to FPGA and tell decompression is necessary or not?

    Thanks very much for your input on this topic.

    BRs,

    Johnson