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Altera_Forum
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17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Johnson,

The S29GLxxxP needs reset before starting access, and time from power-on or reset to 1st access is longer than previous model. I recommend you to make sure that reset signal is connected to the S29GLxxxp and put a counter in the MAX II so that PFL delays first access.

Thanks!