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Altera_Forum
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17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Johnson,

Looking from the simulation result, 40 ns(1 clock) glitch is normal behavior. If you are concerned about PGM pin, please make sure that they are connected directry, without through resister, to GND.

Regards!