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Altera_Forum's avatar
Altera_Forum
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17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi gmpstr,

Thanks for sharing.

I already added that in my current design.

Yes, I could noticed that there are some data moving out from flash to fpga.

But the complete configuration cycle was not finished, I could see nStatus and nCONFIG from Arria pulling high and low to indicate the data has error.

I noticed that the A0 output from MAXII to flash has a 40-ns pulse...as I posted in my previous post.

Anyway I have a improvement from your inputs, thanks a lot!

BRs,

Johnson