Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Gee,

Thanks for your information regarding simulation.

I measure the output pattern of nStatus and A0 and noticed that the 40-ns glitch happened during nSTATUS is low.

Perhaps I have to double check my settings as I tie all PGM pins to GND..

I saw your simulation output, thanks for your data..

That would be of great help if you could provide me your testbench.

BRs,

Johnson