Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FPGA Configuration using CPLD!

Hi all, I have a question need your precious comments. As I create my pcb with a Arria and MAXII. I planned to use Paralle Flash Loader in CPLD to configurate Arria. After following AN3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Did you write the configuration data and the options bits to flash using the NIOSII EDS? Are the options bits at the location that the PFL in the CPLD is looking for them? I just had an issue where I had the PFL core looking at the wrong location in flash for the options bits. Reran the megawizard and reprogrammed flash and it worked great.

As gee said, you need to write a small power-on reset in the cpld design to hold the flash chip in reset for a bit(whatever the data sheet shows). We ran into this when switching from the N part to the P part.