Fmax for generated clock on Cyclone III EP3C120F780C7

Question

Hello,

I'm working on a design which has a 125 MHz input signal. I have a small part in the FPGA which I wanted to clock with 375 MHz. I've created an altpll module using the MegaWizzard Plug-In Manger which is supposed to generate the 375 MHz clock using the 125 MHz input clock signal.

When I look at the Time Quest Timing Analysis Report I can see for the generated clock a Fmax and Restricted Fmax of 149.59 MHz.

Is this the maximum supported frequency for my device or is there anything I can do to generated the needed clock?

Best regards

Martin

altera_forum · Answer

375Mhz is at the top end of speeds supported by the top end devices. In a C3 you'll be lucky to get much over 200MHz.

The FMax is down to the logic design rather than the clock itself. At 375 (if the FPGA will even go that fast, which I highly doubt it will) you have to have very very well designed logic.

altera_forum · Answer

Thanks for clarification!

I already feared that this frequency would be problematic. I was hoping that it could work because the part which is supposed to work at 375 MHz is pretty small. This is a learning project so it's not that problematic.

I've tried to use Time Quest Timing Analyzer to figure out the problematic paths. There are the "From Node" and "To Node" columns in the Report. Is there a way to graphically show the logic which gets synthesized between these two nodes?

altera_forum · Answer

unfortunatly not. But to get those high speeds you need to highly pipeline your design with minimum (1 LUT max) between registers.

altera_forum · Answer

I don't know what your block is supposed to do, but as it is rather small, you may be able to parallelize it, using several blocks running at a fraction of the frequency.

altera_forum · Answer

I think it could be possible to parallize the block. I would need three clock then which have a phase shift of 1/3 of the period.

The module is supposed to synchronize to external signal. The external signal is clocked with a 125 MHz clock and it's recommended to oversample the signal with a 375 MHz clock. The design then synchronizes to the header which is send at the beginning of each data package.

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Fmax for generated clock on Cyclone III EP3C120F780C7

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