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Altera_Forum
Honored Contributor
Honored ContributorFmax for generated clock on Cyclone III EP3C120F780C7
Hello, I'm working on a design which has a 125 MHz input signal. I have a small part in the FPGA which I wanted to clock with 375 MHz. I've created an altpll module using the MegaWizzard Plug-I...
Altera_ForumHonored Contributor
Honored Contributorunfortunatly not.
But to get those high speeds you need to highly pipeline your design with minimum (1 LUT max) between registers.
