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Honored Contributor
Honored ContributorFmax for generated clock on Cyclone III EP3C120F780C7
Hello, I'm working on a design which has a 125 MHz input signal. I have a small part in the FPGA which I wanted to clock with 375 MHz. I've created an altpll module using the MegaWizzard Plug-I...
Altera_ForumHonored Contributor
Honored ContributorI think it could be possible to parallize the block. I would need three clock then which have a phase shift of 1/3 of the period.
The module is supposed to synchronize to external signal. The external signal is clocked with a 125 MHz clock and it's recommended to oversample the signal with a 375 MHz clock. The design then synchronizes to the header which is send at the beginning of each data package.
