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Altera_Forum
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13 years ago

Fmax for generated clock on Cyclone III EP3C120F780C7

Hello, I'm working on a design which has a 125 MHz input signal. I have a small part in the FPGA which I wanted to clock with 375 MHz. I've created an altpll module using the MegaWizzard Plug-I...
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Altera_Forum
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13 years ago

Thanks for clarification!

I already feared that this frequency would be problematic. I was hoping that it could work because the part which is supposed to work at 375 MHz is pretty small. This is a learning project so it's not that problematic.

I've tried to use Time Quest Timing Analyzer to figure out the problematic paths. There are the "From Node" and "To Node" columns in the Report. Is there a way to graphically show the logic which gets synthesized between these two nodes?