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Honored Contributor
Honored ContributorFmax for generated clock on Cyclone III EP3C120F780C7
Hello, I'm working on a design which has a 125 MHz input signal. I have a small part in the FPGA which I wanted to clock with 375 MHz. I've created an altpll module using the MegaWizzard Plug-I...
Altera_ForumHonored Contributor
Honored Contributor@FvM: I guess this means that you have no more than one LUT between two registers?
