fir filter for fsk demodulator

in this way the parameters to pass to filter after the decimator is:

Fs=50KHz;

Fcut=100Hz

Fstop=400Hz

is it right?

Can i use the FIR compiler 2?

--- Quote Start ---

in this way the parameters to pass to filter after the decimator is:

Fs=50KHz;

Fcut=100Hz

Fstop=400Hz

is it right?

Can i use the FIR compiler 2?

--- Quote End ---

No...

Fs is 200KHz

Fcutoff ...etc use same filter I gave you (cuts at 200Hz and achieves -40dB at 6300Hz.

you can use fir compiler. The output will be decimated to 50Ksps on same system clock of 200Khz (as rate of valid out will indicate)

i've implemented in this way but it doesn't work

https://www.alteraforum.com/forum/attachment.php?attachmentid=9134

i surely don't understand very well...

could you explain me better how set the fir compiler correctly?

I don't see a decimator option....

In the fir compiler GUI you will see list of single rate, interpolator/decimator. Then you enter the rate as 1 interpolation, 4 decimation. I don't know about your schematic approach.

once you run fir compiler it generates hdl file.

I had a further look at the design. In fact you can decimate much more.

First your nco should produce the required range and not just for 4050 case.

your worst case is 20KHz signal. you will push it to zero so the other sideband goes to 40Khz which is then filtered followed by decimation.

Hence you can decimate right to cover the 200Hz signal i.e. 400samples per sec or say 1k i.e. decimation rate of 200K/1 = 200.

if you choose this scenario then the filter must cut at 200Hz but sharply at 500Hz instead of 6300 thus it will increase taps but decimation will reduce multipliers by 200

The choice is yours

i try this solution simulating it in simulink but it doesn't work

https://www.alteraforum.com/forum/attachment.php?attachmentid=9140

it works if i put a fir filter after a decimator with FS=50K, Fcut=100 and Fstop=400 but it has 500 taps in order to work correctly...

One last thing that i ommitted: i need to obtain not real demodulation (0 and 1) but also the magnitude of output signal to understand if my input signal is @ full dynamic or not....

Could you check my design and eventually make your corrections? Thanks

i've applied your advise of previous post and it works!!! Great!!!

--- Quote Start ---

i try this solution simulating it in simulink but it doesn't work

https://www.alteraforum.com/forum/attachment.php?attachmentid=9140

it works if i put a fir filter after a decimator with FS=50K, Fcut=100 and Fstop=400 but it has 500 taps in order to work correctly...

One last thing that i ommitted: i need to obtain not real demodulation (0 and 1) but also the magnitude of output signal to understand if my input signal is @ full dynamic or not....

Could you check my design and eventually make your corrections? Thanks

i've applied your advise of previous post and it works!!! Great!!!

--- Quote End ---

Does it work or not? and what do you mean by work or not work? how do you assess that?

To convert two frequencies to zeros and ones you need to get phase, unwrap it and convert to delay (difference of phase). Each tone will have its unique delay as you can see in the phase response of your filter.

square Magnitude = i^2+Q^2 and I don't think you need to square root it and I don't see why you need it at all.

it works with this scheme:

In_fsk --> sin(f0) cos(f0) mixing --> fir decimation with factor 16 with fs=200k and f(-40db)=6.3K --> fir with fs=200k/16 and f(-40db)=400Hz ---> sqrt(I^2+Q^2)

There is one branch for f0 and onother for f1...

Fir decimatior has about 100 taps and the next one has about 80 taps...the advantage is saving resources

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To convert two frequencies to zeros and ones you need to get phase, unwrap it and convert to delay (difference of phase). Each tone will have its unique delay as you can see in the phase response of your filter.

--- Quote End ---

i don't undestand very well this thing or better i dotn't know how implement it in vhdl... how could i get phase from the fir response? Could you explain me better? Sorry but perhaps since the beginning of this discussion the part that it was less clear is exactly convert two frequencies to zero....(it's my fault) :(

Thanks again

if you model two frequencies in Matalb, you can see how to convert them to two levels:

f1 = exp(j*2*pi*(0:1023)*.1);

f2 = exp(j*2*pi*(0:1023)*-.1);

f=[f1 f2]; %two symbols

plot(diff(unwrap(angle(f))),'.-')

the angle is that of I/Q stream. diff is easy (current sample - next sample).

the unwrap and angle are a bit tricky and is usually done in software but you can do it in vhdl by indirect methods. see:

http://www.dspguru.com/dsp/tricks/fixed-point-atan2-with-self-normalization

(http://www.dspguru.com/dsp/tricks/fixed-point-atan2-with-self-normalization)