FIFO Interface

Hello Mike,

Thanks for your very useful contribution. I do however have a question which seems not to be answered by your documentation:

I have created a read fifo (data towards nios) using your tool. On the processor port symbol appears a "clk_en_from_the_readFifo", in addition to the "fifo_rdreq_from_the_readFifo".

I expect that the fifo_rdreq should go to the rdreq input in the fifo (external to nios) which I have generated using the megawizard, but whats the use of clk_en? On the symbol which I have got from the wizard I have no clk_en input.

I browsed your documentation but could not find any mention of this pin. Can you give me a hint?

thanks

Hennnig

Risoe national laboratory

Denmark

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originally posted by larsen@Oct 12 2004, 08:51 AM

i have created a read fifo (data towards nios) using your tool. on the processor port symbol appears a "clk_en_from_the_readfifo", in addition to the "fifo_rdreq_from_the_readfifo".

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That's a side-effect from something I don't quite understand about the undocumented Europa library. There's a vestigial "clk_en" output generated, which always drives a logic 1. It should be left unconnected.

Removing it from the em_fifo.pl script would disable the internal read register. I'm not sure why this is.

Thanks for your reply Mike.

In the software part you have some pretty fancy macros. Would it be posible for you to post some code snippets on how they are intended to be used.

Interrupt use would also be interesting to see.

This would be realy helpfull for me as a new NIOS user.

henning

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originally posted by larsen+oct 13 2004, 05:33 am--><div class='quotetop'>quote (larsen @ oct 13 2004, 05:33 am)</div>

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in the software part you have some pretty fancy macros. would it be posible for you to post some code snippets on how they are intended to be used.[/b]

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the register_bit macro is for use in that header only (to save me typing, clutter, and potential errors); it&#39;s# undef&#39;d on the way out.

that said, the other macros defined are all named the standard altera way, e.g. iord_arlut_fifo_interface_regname(base) reads from a register, and iowr_arlut_fifo_interface_regname(base, value) writes to a register. for the bits in the status register, arlut_fifo_interface_status_bitname_ofst is the bit&#39;s offset, and arlut_fifo_interface_status_bitname_msk is the bit mask. for control register bits, change status to control.

<!--quotebegin-larsen@Oct 13 2004, 05:33 AM

interrupt use would also be interesting to see.

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I haven&#39;t written any interrupt-using code for a couple reasons:[list][*] My current application is so memory-constrained that I don&#39;t have interrupts (everything is polled), so I can&#39;t justify writing interrupt handler code I&#39;m not using,

[*] Assumptions would need to be made that would likely not be valid (for example, I could write a HAL character-device driver, but that can&#39;t work when the FIFO width is greater than 8 bits without extraneous word splitting and merging),

[*] The user will be able to write much better (read: more specialized to their application) code than I can, and

[*] I&#39;m still learning SOPC Builder&#39;s and HAL&#39;s way of doing things.

[/list]If you need a starting point for basic uses, I would recommend looking at the Altera Nios UART driver for a starting point. Anything I wrote would look a lot like that.

If you want more specific help, please contact me by email.

Mike,

Having done some fine-reading on the header file "arlut_fifo_interface_regs.h" and its macro&#39;s followed by a quick simulation I think I finally can contribute constructively to your fifo interface.

The REGISTER_BIT macro should read

#define REGISTER_BIT(regName, bitName, bitNum) 
    ARLUT_FIFO_INTERFACE_##regName##_##bitName##_OFST =   bitNum, 
    ARLUT_FIFO_INTERFACE_##regName##_##bitName##_MSK = (1 << 
  ARLUT_FIFO_INTERFACE_##regName##_##bitName##_OFST)

The original one never takes account of the bitNum parameter (end of second line).

regards

henning

Oi. I fixed that over here, but forgot to upload it. All better now.

Version 0.1.1 attached for your convenience.

I&#39;m trying the fifo interface but for a fifo of 512 words of 32 bits, the fifo has a usew of 9 bits and the fifo interface has a usew of 10 bits. Why? And how can i solve that?

I&#39;m also trying to write on the fifo interface and I can&#39;t. Would you have a demo of using the fifo interface with a DMA on nios ide?

Muffec

Muffec@voila.fr

Sorry for the late reply; I don&#39;t check this board as much as I should. In the future, please email me with your questions; I check that at least every business day.

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originally posted by muffec@Mar 30 2005, 06:41 AM

i&#39;m trying the fifo interface but for a fifo of 512 words of 32 bits, the fifo has a usew of 9 bits and the fifo interface has a usew of 10 bits. why? and how can i solve that?

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I have a guess what&#39;s going on. 512 in hex is 0x200, which requires 10 bits to represent. The FIFO Interface assumes that you can use all memory in the FIFO, not one-less-than-all, so the usedw[] bus would need to be one more bit wider than the memory&#39;s address bus would be.

The solution, if the FIFO stops one element short of full like that, is to set the high bit of usedw[] into the FIFO interface to 0, and if you use the words-free stuff in the FIFO interface, to check the box for "FIFO uses 1 less than all words" (or something to that effect) in the configuration window.

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originally posted by muffec@Mar 30 2005, 06:41 AM

i&#39;m also trying to write on the fifo interface and i can&#39;t. would you have a demo of using the fifo interface with a dma on nios ide?

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I&#39;m not sure what that bug is exactly, but I encountered one like it, although it involved a DMA peripheral talking to something other than a FIFO interface. If I connected a DMA master to only one slave, and that slave had only one register (i.e. no address bus), the DMA would execute but the data wouldn&#39;t be written to the port. The problem was that the Avalon bus master arbitrator for the DMA would send an address of 0 to the slave arbitrator (thinking the address is unused), but the slave was expecting the real address. I don&#39;t know if that bug still exists, or if it applies to the FIFO interface (which does have an address bus). The workaround was to connect the master to slaves which have addresses above and below the slave you&#39;re actually trying to use; I used my ROM (which is at 0) and my RAM (which is at the highest address).

I don&#39;t have code that uses the FIFO interface with the HAL DMA interface in the Nios IDE; I programmed the DMA registers directly. The main rules are to set the DMA address for the FIFO end of the transfer to the base address of the FIFO interface, set the flag for the proper transfer size, and to set the flag that tells the DMA not to increment that address.

Hello

I had the same problem. But the solution is to use the full bit as MSB [full, usedw[] ]. This word give the exact number of words in the fifo.

Thanks to Mike his fifo-Interface works great.

Joerg

weigold@eti.uni-karlsruhe.de

Blocking mode doesn&#39;t work. I&#39;ve attached a fix (a new class.ptf file).

The problem is that when blocking mode is specified, you have to set the Read_Wait_States and Write_Wait_States in the SBI to "peripheral_controlled" for Avalon to honor the waitrequest signal.

To deploy the fix, just overwrite the original class.ptf with this new file, run SOPC Builder, and double-click on all existing instantiations of the component to get the wizard_finish portion of the class.ptf to run, and then regenerate.