FIFO Interface

Sorry for the late reply; I don't check this board as much as I should. In the future, please email me with your questions; I check that at least every business day.

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originally posted by muffec@Mar 30 2005, 06:41 AM

i'm trying the fifo interface but for a fifo of 512 words of 32 bits, the fifo has a usew of 9 bits and the fifo interface has a usew of 10 bits. why? and how can i solve that?

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I have a guess what's going on. 512 in hex is 0x200, which requires 10 bits to represent. The FIFO Interface assumes that you can use all memory in the FIFO, not one-less-than-all, so the usedw[] bus would need to be one more bit wider than the memory's address bus would be.

The solution, if the FIFO stops one element short of full like that, is to set the high bit of usedw[] into the FIFO interface to 0, and if you use the words-free stuff in the FIFO interface, to check the box for "FIFO uses 1 less than all words" (or something to that effect) in the configuration window.

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originally posted by muffec@Mar 30 2005, 06:41 AM

i'm also trying to write on the fifo interface and i can't. would you have a demo of using the fifo interface with a dma on nios ide?

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I'm not sure what that bug is exactly, but I encountered one like it, although it involved a DMA peripheral talking to something other than a FIFO interface. If I connected a DMA master to only one slave, and that slave had only one register (i.e. no address bus), the DMA would execute but the data wouldn't be written to the port. The problem was that the Avalon bus master arbitrator for the DMA would send an address of 0 to the slave arbitrator (thinking the address is unused), but the slave was expecting the real address. I don't know if that bug still exists, or if it applies to the FIFO interface (which does have an address bus). The workaround was to connect the master to slaves which have addresses above and below the slave you're actually trying to use; I used my ROM (which is at 0) and my RAM (which is at the highest address).

I don't have code that uses the FIFO interface with the HAL DMA interface in the Nios IDE; I programmed the DMA registers directly. The main rules are to set the DMA address for the FIFO end of the transfer to the base address of the FIFO interface, set the flag for the proper transfer size, and to set the flag that tells the DMA not to increment that address.