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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error when uploading the code to the FPGA DE2-70

Hi all,

I have followed the example you may find in tut_sopc_introduction_verilog.pdf

Everything goes fine to the point where I need to upload the program...

Then I get the following error :

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: FAILED

Leaving target processor paused

what could have gone wrong?

I used Quartus II 9.0 with free licence and Altera monitor program and an FPGA DE2-70

Thank you in advance

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    When the CPU isn't responding, it can be either because the .sof file hasn't been loaded, it isn't the right .sof file, or one of the critical signals (clock, dada) isn't correct. Check all those points:[list][*]did the project compile successfully?[*]are you using the correct .sof file? If you are missing some licenses, the design could be compiled in a *_time_limited.sof file instead. Check the report[*]did you assign the ports to the correct FPGA pins? Especially reset and clock[*]is the clock running?[*]does the reset signal have the correct polarity. The reset_n pin from the SOPC builder project is active low[/list]

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you for your help,

    I have used a _time_limited.sof file, for the clock i used clk_0 with a 50 Mhz frequency, i don't know if it works well or not. Also, i have used the inport assignmets with the file "DE2_70_assignments.csv",

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    When you see the opencore evaluation window, it is very important not to close it. If you do then the CPU will stop working.

    Do you have a .sdc file with the timing constraints? The bare minimum would be one with a line that defines your clock input, although if you are using 50MHz without a pll you shouldn't run into too much timing problems yet.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes, i have an sdc file, you find this file joined to this email, i don't close the opencore evaluation window. I put only one sdc file in the project ?

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This is only the sdc file generated with the CPU. I think it is automatically added in the project with the .qip file.

    You need to create another .sdc file that defines your clocks. Are you using any pll?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    Yes i have created an other sdc file "filref.sdc", in which were defined the clocks, i don't use any pll. You find also the Fils "DE2-70-assignemets.csv" and "lights.v".

    Thank you for your help
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I think your clock in the .sdc file has the wrong name, you should use iCLK_50. Don't you have any complaints from Timequest?

    How is your iKEY signal generated? I don't see it in your code. Don't forget that the reset_n signal is active low, so must be at 1 for the CPU to run.