Error when uploading the code to the FPGA DE2-70

When the CPU isn't responding, it can be either because the .sof file hasn't been loaded, it isn't the right .sof file, or one of the critical signals (clock, dada) isn't correct. Check all those points:[list][*]did the project compile successfully?[*]are you using the correct .sof file? If you are missing some licenses, the design could be compiled in a *_time_limited.sof file instead. Check the report[*]did you assign the ports to the correct FPGA pins? Especially reset and clock[*]is the clock running?[*]does the reset signal have the correct polarity. The reset_n pin from the SOPC builder project is active low[/list]