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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error when uploading the code to the FPGA DE2-70

Hi all, I have followed the example you may find in tut_sopc_introduction_verilog.pdf Everything goes fine to the point where I need to upload the program... Then I get the following ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

This is only the sdc file generated with the CPU. I think it is automatically added in the project with the .qip file.

You need to create another .sdc file that defines your clocks. Are you using any pll?