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Altera_Forum
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14 years ago

Error when uploading the code to the FPGA DE2-70

Hi all, I have followed the example you may find in tut_sopc_introduction_verilog.pdf Everything goes fine to the point where I need to upload the program... Then I get the following ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

When you see the opencore evaluation window, it is very important not to close it. If you do then the CPU will stop working.

Do you have a .sdc file with the timing constraints? The bare minimum would be one with a line that defines your clock input, although if you are using 50MHz without a pll you shouldn't run into too much timing problems yet.