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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error when uploading the code to the FPGA DE2-70

Hi all, I have followed the example you may find in tut_sopc_introduction_verilog.pdf Everything goes fine to the point where I need to upload the program... Then I get the following ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think your clock in the .sdc file has the wrong name, you should use iCLK_50. Don't you have any complaints from Timequest?

How is your iKEY signal generated? I don't see it in your code. Don't forget that the reset_n signal is active low, so must be at 1 for the CPU to run.