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Altera_Forum's avatar
Altera_Forum
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14 years ago

Error when uploading the code to the FPGA DE2-70

Hi all, I have followed the example you may find in tut_sopc_introduction_verilog.pdf Everything goes fine to the point where I need to upload the program... Then I get the following ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you for your help,

I have used a _time_limited.sof file, for the clock i used clk_0 with a 50 Mhz frequency, i don't know if it works well or not. Also, i have used the inport assignmets with the file "DE2_70_assignments.csv",

Thank you