Error in signal assignment with VHDL

I'm trying to create a simple register connected to a 8-width bidirectional bus. But when I read a value from this bus and write it back, some of these bits receive don't care value, while others are ok. I didn't understand that since I don't deal with these bits individually. Someone could help?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity reg is
    generic(
        MAX_COUNT: in natural := 8);
    port(data: inout std_logic_vector(MAX_COUNT-1 downto 0);
         incr,decr,lr,erd: in bit;
         clk: in std_logic);
end entity;
architecture behavioral of reg is
signal out_r: std_logic_vector(MAX_COUNT-1 downto 0);
begin
    process(clk)
    
    variable var: std_logic_vector(MAX_COUNT-1 downto 0);
    
    begin
        if rising_edge(clk) then
            if lr = '1' then
                var := data;
            end if;
            if incr = '1' then
                var := var+1; 
            end if;
            if decr = '1' then
                var := var-1; 
            end if;
            out_r <= var;
        end if;
    end process;
    
    process(clk,erd)
    begin   
       if rising_edge(clk) then
         if erd = '1' then
           data <= out_r;
         else
           data <= (others => 'Z');
         end if;
       end if;
    end process;
end architecture;