Error in signal assignment with VHDL

First things first. A 'X' is not a don't care for std_logic signals. A don't care is '-'.

What you see is two active bus drivers (one is your testbench and the other your design) are active at the same time and driving different values against each other.

Ok to explain what happens lets go through your simulation step by step:

time = 0 ns (start of simulation)

your testbench sets

incr = '1'

decr = '0'

lr = '0'

erd = '0'

data = 185

your logic does

out_r = "UUUUUUUU" (no assignment at declaration)

data = "UUUUUUUU" (no assignment at declaration) and the testbench drives 185 here is a conflict and you get "XXXXXXXX"

time = 5 ns (rising clock edge)

your logic does

out_r = "UUUUUUUU" + 1 = "XXXXXXXX"

data = "ZZZZZZZZ" therefore the testbench driver wins and you see 185

time = 10 ns (testbench changes)

your testbench sets

incr = '0'

decr = '1'

lr = '1'

erd = '0'

data = 114

time = 15 ns (rising clock edge)

your logic does

out_r = 114 - 1 = 113

data = "ZZZZZZZZ" therefore the testbench driver wins and you see 114

time = 20 ns (testbench changes)

your testbench sets

incr = '0'

decr = '0'

lr = '1'

erd = '1'

data = 101

time = 25 ns (rising clock edge)

your logic does

out_r = 101

data = previous out_r = 113 ("0111 0001") driving against 101 ("0110 0101") resulting in ("011X 0X01")

and so on.