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Altera_Forum
Honored Contributor
Honored ContributorError in signal assignment with VHDL
I'm trying to create a simple register connected to a 8-width bidirectional bus. But when I read a value from this bus and write it back, some of these bits receive don't care value, while others are...
Altera_ForumHonored Contributor
Honored ContributorI know that. It's not going to be implemented on hardware (maybe in the future). The project is an assynchronous microprocessor only for learning purposes. Anyway, thank you all people.
