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Altera_Forum
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13 years ago

Error in signal assignment with VHDL

I'm trying to create a simple register connected to a 8-width bidirectional bus. But when I read a value from this bus and write it back, some of these bits receive don't care value, while others are...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I hope that your INOUT signal is going to the pins of the FPGA. Then there are no tri-state drivers inside the FPGA internal logic. Only the I/O's have tri-state drivers.