Error (16021) using 10M08SCE144C8G

Hi,
I checked which errors are raised in which situation.

You get error 16021 if you try to compile 10MxxSC with memory initialization configuration.
Compiling a design with initialized RAM but without respective configuration gives error 16031.

If you continuously get error 16021, you didn't manage to change the configuration. You can check project .qsf, it should e.g. contain an assignment
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"

Your problem might be caused by a strange behaviour of the Device and Pin Options dialog. The displayed Configuration Mode does not necessary reflect the actual setting because it only shows legal values for the selected device. You need to change it to a different option and back to the intended setting to change the internal value.

I stated above that SC type can't implement lookup tables. That's not fully correct, it can't implement lookup table defined as initialized block ram (altsyncram IP). It compiles however inferred ROM without problems, except for a possibly large lcell utilisation.

Dear FvM,

I would like to express my gratitude for addressing my queries.

1) Compilation Results:

I performed compilations with both 10M16SCE and 10M08SCE devices, yielding notable differences in outcomes.

For the 10M16SCE144C8G device, the compilation using Single Uncompressed Image (256Kbits UFM) was successful, as evidenced by the following details:

"----

Flow Status Successful - Thu Jan 25 17:47:39 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M16SCE144C8G
Timing Models Final
Total logic elements 7,807 / 15,840 ( 49 % )
Total registers 1088
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 562,176 ( 0 % )
Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )
----"

However, reverting to the 10M08SCE144C8G device (with Single Uncompressed Image (256Kbits UFM)) resulted in a failure, requiring 11,504 logic elements, exceeding the device's capacity:

"------
Flow Status Flow Failed - Fri Jan 26 11:27:49 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 11,504 / 8,064 ( 143 % )
Total registers 1196
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 387,072 ( 0 % )
Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )
------"

Furthermore, attempting to compile with "Single Compressed Image (720Kbits UFM)" on the 10M08SCE144C8G device also failed, displaying Error 16021. The details are as follows:

2) .qsf File Modification:

As you pointed out, there is a line in the .qsf file that reads "set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE." What steps should I take about this line?

3) Workaround Implementation:

This link
https://www.intel.com/content/www/us/en/support/programmable/articles/000074796.html?erpm_id=6573007_ts1706295120833
suggested a workaround:

"-------
Resolution
Signal declaration for memory_type should be changed from

signal mem : memory_type :=(others => (others => '0'));

to

signal mem : memory_type;

This is to ensure that memory is not initialized and there is no compilation error in the Assembler stage.
------"

I'm using Verilog language and am not sure how to implement this workaround.

Once again, thank you for your assistance.

Hi FvM,

I appreciate your prompt response to my inquiries.

As you pointed out, the .qsf file contains the line

"set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE".

What steps should I take about this?

I came across a suggested workaround on this link:

It suggests a workaround:

"-----
Resolution
Signal declaration for memory_type should be changed from

signal mem : memory_type :=(others => (others => '0'));

to

signal mem : memory_type;

This is to ensure that memory is not initialized and there is no compilation error in the Assembler stage.
-----"

Since I am using Verilog, could you guide me on how to implement this workaround?

Thank you once again.

Hi,

The workaround are using VHDL. You can just convert it to verilog.

Regards,

Aiman

Hi,

To answer your question;

1. If it is for core logic cell, your understanding is not correct.
2. Please provide compilation report for this so we are able to analyze this further.

Regards,

Aiman

Hi Alex, Do you have updates from previous request?

regards,

Farabi

Hi,

1. What is the setting when compiling those 2 devices? Is there any differences? (Compilation setting)
2. Please also share the compilation report for 10M016SCE144C8G.
3. Can you share your design in .qar?

Regards,

Aiman

Hi,

.qar file is basically an archived file. You may refer below for the steps;

https://www.intel.com/content/www/us/en/docs/programmable/683463/21-3/archiving-projects-for-service-requests.html

Regards,

Aiman

Hi,

Per our observation based on the compilation report, the error occur when using 10M08SCE144C8G is because the device does not support your design.

As you can see from the compilation report, the design has used all the Embedded Multiplier 9-bit elements 48 / 48 ( 100 % ), which is not enough for 10M08SC as the design need more hence it overused the Total logic elements 11,504 / 8,064 ( 143 % ) - , thus compilation is failed.

Family MAX 10

Device 10M08SCE144C8G

Timing Models Final

Total logic elements 11,504 / 8,064 ( 143 % )

Total registers 1196

Total pins 32 / 101 ( 32 % )

Total virtual pins 0

Total memory bits 0 / 387,072 ( 0 % )

Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )

Total PLLs 0 / 1 ( 0 % )

UFM blocks 0 / 1 ( 0 % )

ADC blocks 0

Your design need to use bigger device which is 10M16SCE144C8G that is suitable with your design.

Family MAX 10

Device 10M16SCE144C8G

Timing Models Final

Total logic elements 7,786 / 15,840 ( 49 % )

Total registers 1088

Total pins 32 / 101 ( 32 % )

Total virtual pins 0

Total memory bits 0 / 562,176 ( 0 % )

Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )

Total PLLs 0 / 1 ( 0 % )

UFM blocks 0 / 1 ( 0 % )

ADC blocks 0

Regards,

Aiman