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alex100
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2 years ago

Error (16021) using 10M08SCE144C8G

I'm utilizing the MAX10 FPGA, specifically the 10M08SCE144C8G model, to generate sweeping sinewave signals using lookup tables and multipliers. However, during compilation, I encountered the followin...
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alex100's avatar
alex100
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2 years ago

Dear FvM,

I would like to express my gratitude for addressing my queries.

1) Compilation Results:

I performed compilations with both 10M16SCE and 10M08SCE devices, yielding notable differences in outcomes.

For the 10M16SCE144C8G device, the compilation using Single Uncompressed Image (256Kbits UFM) was successful, as evidenced by the following details:

"----

Flow Status Successful - Thu Jan 25 17:47:39 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M16SCE144C8G
Timing Models Final
Total logic elements 7,807 / 15,840 ( 49 % )
Total registers 1088
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 562,176 ( 0 % )
Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )
----"

However, reverting to the 10M08SCE144C8G device (with Single Uncompressed Image (256Kbits UFM)) resulted in a failure, requiring 11,504 logic elements, exceeding the device's capacity:

"------
Flow Status Flow Failed - Fri Jan 26 11:27:49 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 11,504 / 8,064 ( 143 % )
Total registers 1196
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 0 / 387,072 ( 0 % )
Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )
------"

Furthermore, attempting to compile with "Single Compressed Image (720Kbits UFM)" on the 10M08SCE144C8G device also failed, displaying Error 16021. The details are as follows:

"-----
Flow Status Flow Failed - Fri Jan 26 10:57:35 2024
Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Revision Name Ramp50M
Top-level Entity Name Ramp50M
Family MAX 10
Device 10M08SCE144C8G
Timing Models Final
Total logic elements 5,815 / 8,064 ( 72 % )
Total registers 1107
Total pins 32 / 101 ( 32 % )
Total virtual pins 0
Total memory bits 92,672 / 387,072 ( 24 % )
Embedded Multiplier 9-bit elements 48 / 48 ( 100 % )
Error (16021): You specified a configuration mode that includes memory initialization, however memory initialization is not supported by the selected device. In the Device and Pin Options dialog box, choose a configuration mode without memory initialization.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Error (171000): Can't fit design in device
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 4961 megabytes
Error: Processing ended: Fri Jan 26 10:57:35 2024
Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:04
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 147 warnings
----"

2) .qsf File Modification:

As you pointed out, there is a line in the .qsf file that reads "set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE." What steps should I take about this line?

3) Workaround Implementation:

This link
https://www.intel.com/content/www/us/en/support/programmable/articles/000074796.html?erpm_id=6573007_ts1706295120833
suggested a workaround:

"-------
Resolution
Signal declaration for memory_type should be changed from

signal mem : memory_type :=(others => (others => '0'));

to

signal mem : memory_type;

This is to ensure that memory is not initialized and there is no compilation error in the Assembler stage.
------"

I'm using Verilog language and am not sure how to implement this workaround.

Once again, thank you for your assistance.